Information processing system

ABSTRACT

The object of this invention is to perform the sorting, compiling and joining of data at extremely high speeds. This is achieved by a distributed memory type information processing system comprising: a CPU module, a plurality of memory modules, each of which having a processor and RAM core, and a plurality of sets of buses that make connections between the CPU and memory modules and/or connections among memory modules, where the processors of the various memory modules execute the processing of arrays managed by the one or more memory modules based on instructions given by the CPU to the processors of the various memory modules. In this system, the processor of the memory module comprises: sorting means that executes a sort on the elements that make up those portions of the array that it itself manages, and reorders the elements according to a specific order, I/O that, depending on the positions that the portions managed by itself occupy within the array, sends the sorted elements together with their sequence numbers to another memory module via a stipulated bus, or receives the elements and sequence numbers from another memory module via a stipulated bus, sequence number calculation means that, upon receipt of the element and sequence number, compares it with the elements that it manages itself and calculates a virtual sequence number which is a candidate for the sequence number of the received element, and returns it to the other memory module, and sequence determination means that, upon receipt of the virtual sequence number, determines the sequence of elements according to the virtual sequence numbers. Thus, the sequence numbers of elements of the array are determined by means of communication between a presentation memory module on the side that sends the element and sequence number and a determination memory module on the side that receives the element and sequence number and calculates the virtual sequence number.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a distributed memory-type informationprocessing apparatus, and particularly to an information processingapparatus that is able to perform the sorting, compiling and joining ofdata at extremely high speeds.

2. Description of the Prior Art

Now that computers have been introduced into many aspects of society inits entirely and the Internet and other networks have become pervasive,data is being accumulated on a large scale. Vast amounts of computingpower is required in order to process data on such large scales, soattempts to introduce parallel processing are natural.

Now, parallel processing architectures are divided into “shared memory”types and “distributed memory” types. The former (“shared memory” types)are architectures wherein a plurality of processors shares a singleenormous memory space. In this architecture, traffic between the groupof processors and the shared memory becomes a bottleneck, so it is noteasy to construct practical systems that use more than 100 processors.Accordingly, at the time of calculating the square roots of 1 billionfloating-point numbers, for example, processing can be performed nofaster than 100 times the speed of a single CPU. Empirically, the upperlimit is found to be roughly 30 times.

In the latter (“distributed memory” types), each processor has its ownlocal memory and these are linked to construct a system. With thisarchitecture, it is possible to design a hardware system thatincorporates even several hundred to tens of thousands of processors.Accordingly, at the lime of calculating the aforementioned square rootsof 1 billion floating-point numbers, processing can be performed severalhundred times to tens of thousands of times the speed of a single CPU.

Latent demand for parallel processing implemented by a large number ofprocessors numbering in the range of several hundred or more is said tobe large, but as described above, these are difficult to design usingarchitectures other than the distributed memory type when they are to beimplemented using current realistic hardware technology.

In distributed memory architectures, the capacity of the memory attachedto the individual processors is small, so in the storage and processingof data (typically in arrays) on a large scale which is one of the mainobjects of parallel processing, it is necessary to divide this dataamong the plurality of processors and the memory attached to each.

However, when arrays are divided among a plurality of processors and thememory attached to each, bus mastering to prevent the collision of dataupon the bus becomes difficult, so if the various processors cannotoperate in parallel, then there is a problem in that the efficiency ofprocessor usage cannot be increased and it is not possible to increasethe speed of processing. To this end, the present invention achievesvarious objects as described below.

-   (1) Collision of data on the bus algorithmically cannot occur so bus    mastering is unnecessary; thereby the processing speed can be    increased by making full use of the bus bandwidth.-   (2) Parallel processing is possible by combining a plurality of    memory modules equipped with a processor (or preferably a plurality    of processors) and memory, and it is possible for the respective    memory modules to be used effectively and processing can be    allocated independently to processors within each memory module, and    thereby processing speed can be further increased by the effective    utilization of memory modules.-   (3) If the size of data subject to sorting is N, then a data size of    only O(N) is required. (With conventional sorting, a data size of    O(N*N) or O(N*Log(N)) is necessary in the worst case.)-   (4) The processing time is stable and even in the worst case, a    predictable processing speed is guaranteed.

To wit, the present invention has as its object to provide aninformation processing apparatus that is able to perform the sorting ofarrays at extremely high speed and with stable processing times.

SUMMARY OF THE INVENTION

An object of the present invention is achieved by a distributed memorytype information processing system comprising: a CPU module, a pluralityof memory modules, each of which having a processor and RAM core, and aplurality of sets of buses that make connections between said CPU andmemory modules and/or connections among memory modules, where theprocessors of the various memory modules execute the processing ofarrays managed by the aforementioned one or more memory modules based oninstructions given by the CPU to the processors of the various memorymodules, and wherein said information processing system is characterizedin that the processor of said memory module comprises: sorting meansthat executes a sort on the elements that make up those portions of thearray that it itself manages, and reorders said elements according to aspecific order, I/O that, depending on the positions that said portionsmanaged by itself occupy within the array, sends said sorted elementstogether with their sequence numbers to another memory module via astipulated bus, or receives said elements and sequence numbers fromanother memory module via a stipulated bus, sequence number calculationmeans that, upon receipt of said element and sequence number, comparesit with the elements that it manages itself and calculates a virtualsequence number which is a candidate for the sequence number of thereceived element, and returns it to said other memory module, andsequence determination means that, upon receipt of said virtual sequencenumber, determines the sequence of elements according to said virtualsequence numbers; such that the sequence numbers of elements of saidarray are determined by means of communication between a presentationmemory module on the side that sends said element and sequence numberand a determination memory module on the side that receives said elementand sequence number and calculates the virtual sequence number.

By means of the present invention, the presentation of elements andsequence numbers by a presentation memory module is executed via a busand virtual sequence numbers are calculated by a determination memorymodule, and these virtual sequence numbers are given to the presentationmemory module via another bus. Accordingly, sorting can proceed inparallel in the presentation memory module and determination memorymodule, and bus collisions can be averted.

In a preferred embodiment of the present invention, said memory modulecomprises: element identification/sending means that identifies elementssubject to processing according to the determined sequence number andsends it over one of the buses, element comparison means that comparesthe previous element subject to processing against the sent element, andan identical-value counter that indicates the count of identicalelements and whose value is incremented when an identical element issent; wherein said element comparison means is constituted such thatwhen the previous element subject to processing is determined to bedifferent from the sent element, the previous element subject toprocessing is associated with the value of the identical-value counterrelated to the element in question and one of which is sent, andmoreover, one of the memory modules receives the previous elementsubject to processing and the value of the related counter thus sent,and is provided with an array in which they are associated and placed inthe order received.

By means of this embodiment, in one of the memory modules, the elementsand their redundancy are received in a stipulated sequence and therebyit is possible to create a non-redundant array of elements and count ofthe various elements. To wit, a non-redundant list of elements and thenumbers of each of the elements in the original array can be easilydetermined thereby.

In another preferred embodiment of the present invention, said memorymodule comprises: a value-number counter that indicates thenon-redundant sequence numbers, whose value is incremented in the eventthat said element comparison means determines that the previous elementsubject to processing is different from the sent element, and sequencenumber updating means that, regarding the sent element, if the previouselement subject to processing is identical to the sent element, sets thevalue of the value-number counter as the sequence number of thenon-redundant element in question, but if they are different, sets theincremented value of the value-number counter as the sequence number ofthe non-redundant element in question.

By means of this embodiment, it is possible to convert the sequencenumbers applied to the elements of the array to one in the state whereinredundancy of elements is eliminated.

In addition, an object of the present invention is achieved by a methodof sorting arrays using a distributed memory type information processingsystem comprising: a CPU module, a plurality of memory modules, each ofwhich having a processor and RAM core, and a plurality of sets of busesthat make connections between said CPU and memory modules and/orconnections among memory modules, where the processors of the variousmemory modules execute the processing of arrays managed by theaforementioned one or more memory modules based on instructions given bythe CPU to the processors of the various memory modules, wherein saidmethod of sorting comprises:

-   (a) a step of sorting the elements that make up those portions of    the array that it itself manages in the memory module,-   (b) a step of, depending on the positions that said portions managed    by itself occupy within the array, determining, among the memory    modules that manage portions of said array, a presentation memory    module on the side that sends the element and sequence number, and a    determination memory module on the side that receives said element    and sequence number,-   (c) a step of, in the presentation memory module, transmitting the    sorted element together with its sequence number to the other memory    module via a stipulated bus,-   (d) a step of, in the determination memory module, receiving said    element and its sequence number from the other memory module via a    stipulated bus,-   (e) a step of, in said determination memory module, based on the    sequence numbers of elements managed by said determination memory    module, calculating a virtual sequence number that indicates a    candidate for the sequence number of the received element, and    returning said virtual sequence number to said presentation memory    module, and-   (f) a step of, in said presentation memory module, upon receiving    said virtual sequence number, updates the sequence number of the    element according to said virtual sequence number, and-   (g) upon each completion of said steps (d) through (f), by taking    each of the memory module groups consisting of the presentation    memory module and determination memory module pertaining to the    element that is given a stipulated sequence number by means of said    steps (d) through (f) as one of the presentation memory module group    and determination memory module group, respectively, and repeating    steps (d) through (f) to update the sequence numbers of elements in    each memory module group, the sequence numbers of each element of    the array are determined.

By means of the present invention, the calculation in the presentationmemory module, sending of elements and sequence numbers in thepresentation memory module, calculation in the determination memorymodule group and sending of virtual sequence numbers in the presentationmemory module can be performed in parallel, and bus collisions can beaverted. To wit, it is possible to achieve the sorting (assignment ofsequence numbers to the elements of the array) at extremely high speeds.In addition, the data size in memory can be kept to only O(N).

In a preferred embodiment of the aforementioned present invention, step(e) comprises:

-   (e1) a step of calculating the virtual sequence number based on a    forward insertion number that indicates the number of elements to be    inserted in front of the received element, the sequence number    regarding the element to be positioned in front, and the received    sequence number.

In a further preferred embodiment of the aforementioned presentinvention, step (f) comprises:

-   (f1) a step of setting the received virtual sequence number to the    sequence number of the element sent in step (c).

A preferred embodiment of the present invention further comprises:

-   (h) a step of, in said presentation memory module, calculating the    redundancy which indicates how many elements managed by memory    modules that make up said presentation memory module group are    present within said memory module group,

wherein said step (c) comprises:

-   (c1) a step of transmitting the sorted element together with its    sequence number and redundancy to the other memory module so that    identical elements are not transmitted redundantly,

wherein said step (e) comprises:

-   (e1) a step of calculating the virtual sequence number based on a    forward insertion number that indicates the number of elements to be    inserted in front of the received element, the sequence number    regarding the element to be positioned in front, and the received    sequence number and redundancy, and

wherein said step (f) comprises:

-   (f2) a step of deciding the sequence number of the element identical    to the element in question based on the difference between the    virtual sequence number and the sequence number at the time of    sending of the element in step (c).

By means of the present invention, there is no need for the presentationmemory module to send the same element multiple time. In addition, whenthe redundancy of a certain element is calculated, it is possible tosend the sequence numbers and redundancy of the element in question tothe judgment memory module, and in the determination memory module, thecalculation of a virtual sequence number for the element in question canbe executed. To wit, this can prevent a decrease in the efficiency ofutilization of the memory modules.

In a further preferred embodiment, the presentation memory module isinitially an independent memory module and the receiving module is alsoan independent memory module, and the presentation memory module groupconsists of 2^(n) memory modules where n (n: an integer greater than orequal to 1) is incremented each time steps (d) through (t) are complete,while the determination memory module group consists of 2^(n) memorymodules.

As described above, the sorting can be achieved ideally when 2^(n)memory modules are used.

In addition, another embodiment of the present invention is a compilingmethod wherein an array is sorted by means of the aforementioned sortingmethod, and based on said sorted array, a new array is generated suchthat the elements within said array are placed in the stipulated orderwithout duplication, and wherein said compiling method comprises:

-   (i) a step of, in the stipulated memory module, sending the elements    subject to processing according to the sequence number,-   (j) a step of, if the previous element subject to processing is    identical to the sent element, incrementing the identical-value    counter that indicates the count of the identical elements present,    but if an element different from the previous element subject to    processing was sent, associating the previous element subject to    processing with the value of the identical-value counter related to    the element in question and sending these,-   (k) a step of receiving the previous element subject to processing    and the value of the associated identical-value counter, and    generating a new array which has them associated, and-   (l) repeating steps (i) through (j) to place the elements and their    counts such that they are associated in said new array.

In addition, the aforementioned compiling method may further comprise:

-   (m) a step of, in one of the modules, monitoring the element sent in    step (j) and the value of the associated identical-value counter,

wherein step (k) is executed by means of one of said modules.

In addition, the aforementioned compiling method may further comprise:

-   (n) a step of, in the memory modules that manage the elements of    said array, providing a sequence-number counter and identical-value    counter that hold the sequence number of the element subject to    processing and the count of said elements, respectively, and also    providing a register that temporarily stores the previous element    subject to processing,-   (o) a step of, in the memory module that manages the element having    the sequence number in question, sending the element in question    according to the sequence number,-   (p) a step of, in the memory module that manages the elements of the    array, comparing the received element and the content of the    register, and if these are identical, incrementing the count, but if    they are not identical, sending the content of the register and the    value of the counter over the second bus, and then updating the    content of the register and the value of the counter,-   (q) a step of, in one of the memory modules, placing the content of    said register and the value of said counter as the element and count    of said elements, respectively, in the array.

In addition, step (n) may further comprise:

-   (n1) a step of providing a value counter that stores non-redundant    sequence numbers for elements subject to processing, and said    step (p) preferably comprises:-   (p1) a step of comparing the received element and the content of the    register, and if these are identical, assigning the value of the    value-number counter as the sequence number of said element subject    to processing, but if they are not identical, incrementing the    value-number counter, and assigning the value of the incremented    value-number counter as the sequence number of said element subject    to processing.

In addition, in another embodiment of the present invention, a method ofjoining arrays achieves the joining of a plurality of arrays using theaforementioned sorting method and the aforementioned compiling method,wherein said joining method comprises:

-   (r) a step of merging a plurality of arrays and executing the    processing of said sorting method by assigning sequence numbers to    each of the elements in these arrays, and-   (s) a step of executing the processing of said compiling method    according to the elements within said merged array and their    sequence numbers, thereby generating a new array with no redundant    elements present.

To wit, by performing the sorting and compiling according to the presentinvention in the state in which the desired arrays are merged, it ispossible to obtain a joined array with redundancy of elementseliminated.

In an even further embodiment, a method of joining arrays achieves thejoining of a plurality of arrays using the aforementioned sorting methodand the aforementioned compiling method using a distributed memory typeinformation processing system comprising: a CPU module, a plurality ofmemory modules, each of which having a processor and RAM core, and aplurality of sets of buses that make connections between said CPU andmemory modules and/or connections among memory modules, where theprocessors of the various memory modules execute the processing ofarrays managed by the aforementioned one or more memory modules based oninstructions given by the CPU to the processors of the various memorymodules, wherein

said memory modules each comprises a pointer array in which pointervalues indicating a value list are placed at positions corresponding tothe record number in order to specify stipulated elements in the valuelist which is an array that stores elements based on the record number,

and said method of joining comprises:

-   (r1) a step of merging a plurality of value lists and executing the    processing of said sorting method by assigning sequence numbers to    each of the elements in these arrays, and-   (t) a step of executing the processing of said compiling method    according to the elements within said merged value list and their    sequence numbers, thereby generating a new array with no redundant    elements present and also updating the sequence numbers of said    elements to the sequence numbers of said elements in the case that    no redundant elements are present, and-   (u) a step of setting said array consisting of sequence numbers of    elements in the case in which no redundant elements are present as a    new pointer array for indicating the new value list.

BRIEF EXPLANATION OF THE DRAWINGS

This and other objects of the present invention will be made clear inreference to the appended drawings and embodiments. Here:

FIG. 1 is a block diagram showing the configuration of a computer systemaccording to an embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a memory module according tothis embodiment.

FIG. 3 is a diagram used to describe pipeline processing among memorymodules according to this embodiment.

FIGS. 4A to 4C are diagrams used to describe the structure of memorymodule 14 under the multi-space memory according to this embodiment.

FIGS. 5A to 5C are diagrams used to describe access to memory modulesaccording to this embodiment.

FIGS. 6A to 6C are diagrams showing one example of an array on which thesorting according to Embodiment 1 is performed.

FIG. 7 is a flowchart showing the procedure for sorting according toEmbodiment 1.

FIG. 8 is a block diagram showing the connections among memory modulesat the time of performing sorting according to Embodiment 1.

FIG. 9 is a schematic diagram showing the connections among the memorymodules shown in FIG. 8.

FIGS. 10A to 10D are diagrams showing the numbering of elements withinan array in the sorting according to Embodiment 1.

FIGS. 11A to 11D are diagrams showing the sequence numbering of elementswithin an array in the sorting according to Embodiment 1.

FIGS. 12A to 12C are diagrams showing the numbering of elements withinan array in the sorting according to Embodiment 1.

FIGS. 13A to 13C are flowcharts that show the sequential numbering amongmemory module pairs according to Embodiment 1.

FIGS. 14A and 14B are block diagrams showing examples of connectionsamong two memory module groups pertaining to the memory modules shown inFIG. 8.

FIGS. 15A and 15B are schematic diagrams showing examples of theconnections shown in FIG. 14.

FIGS. 16A and 16B are diagrams showing the sequence numbering ofelements within an array in the sorting according to Embodiment 1.

FIGS. 17A and 17B are diagrams showing the sequence numbering ofelements within an array in the sorting according to Embodiment 1.

FIGS. 18A and 18B are diagrams showing the sequence numbering ofelements within an array in the sorting according to Embodiment 1.

FIGS. 19A and 19B are diagrams showing the sequence numbering ofelements within an array in the sorting according to Embodiment 1.

FIG. 20 is a diagram used to describe the combination of memory modulesin the sorting according to Embodiment 1.

FIG. 21 is a diagram showing an example of the connection of memorymodules in the case of generating a new array according to the sequencenumbers obtained as a result of the sorting according to Embodiment 1.

FIG. 22 is a diagram showing another example of the connection of memorymodules in the case of generating a new array according to the sequencenumbers obtained as a result of the sorting according to Embodiment 1.

FIG. 23 is a schematic diagram showing an example of the connection ofmemory modules in the sorting according to Embodiment 2.

FIG. 24 is a diagram used to describe the process of calculating theredundancy in memory module groups according to Embodiment 2.

FIG. 25 is a diagram used to describe the process of calculating theredundancy in memory module groups according to Embodiment 2.

FIG. 26 is a flowchart showing the process of calculating the redundancyin memory module groups according to Embodiment 2.

FIG. 27 is a diagram used to describe the process of calculating theredundancy in memory module groups according to Embodiment 2.

FIGS. 28A and 28B are diagrams used to describe the process ofcalculating the redundancy in memory module groups according toEmbodiment 2.

FIGS. 29A and 29B are diagrams used to describe the process ofcalculating the redundancy in memory module groups according toEmbodiment 2.

FIGS. 30A and 30B are diagrams used to describe the process ofcalculating the redundancy in memory module groups according toEmbodiment 2.

FIGS. 31A to 31C are flowcharts showing sorting with the sending ofredundant elements omitted.

FIG. 32 is a schematic diagram showing an example of the connection ofmemory modules in the compiling according to Embodiment 3 of the presentinvention.

FIG. 33 is a flowchart showing the compiling according to Embodiment 3of the present invention.

FIGS. 34A and 34B are diagrams used to describe compiling in the memorymodule group according to Embodiment 3 of the present invention.

FIGS. 35A and 35B are diagrams used to describe compiling in the memorymodule group according to Embodiment 3 of the present invention.

FIGS. 36A and 36B are diagrams used to describe compiling in the memorymodule group according to Embodiment 3 of the present invention.

FIGS. 37A and 37B are diagrams used to describe compiling in the memorymodule group according to Embodiment 3 of the present invention.

FIG. 38 is a diagram used to describe compiling in the memory modulegroup according to Embodiment 3 of the present invention.

FIGS. 39A and 39B are diagrams used to describe compiling in the memorymodule group according to Embodiment 3 of the present invention.

FIG. 40 is a flowchart showing joining according to Embodiment 4 of thepresent invention.

FIGS. 41A and 41B are diagrams used to describe joining in the memorymodule group according to Embodiment 4 of the present invention.

FIGS. 42A to 42C are diagrams used to describe joining in the memorymodule group according to Embodiment 4 of the present invention.

FIGS. 43A and 43B are diagrams used to describe joining in the memorymodule group according to Embodiment 4 of the present invention.

FIGS. 44A and 44B are diagrams used to describe joining in the memorymodule group according to Embodiment 4 of the present invention.

FIG. 45 is a schematic diagram showing the connection of memory modulegroups in another practical example of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[Hardware Configuration]

Here follows a description of the embodiments of the present inventionmade with reference to the appended drawings. FIG. 1 is a block diagramshowing the configuration of a computer system according to anembodiment of the present invention. As shown in FIG. 1, a computersystem 10 comprises a CPU module 12 that performs parallel operationsbased on a single instruction, memory modules 14-1, 14-2 and 14-3 thatstore various types of data required for parallel operations, a harddisk drive 16 that stores required programs and data, a keyboard, mouseor other input device 18, display 20 consisting of a CRT or the like andlegacy memory 22 that stores data and the like in various formats. Inaddition, on buses 24-1, 24-2, . . . , switches 28-1, 28-2, 28-3, . . .and the like are placed at points of contact with the various memorymodules 14, so the selected circuit elements are able to exchangeinformation. In addition, switches 30-1, 30-2, . . . are providedbetween the CPU module 12 and memory module 14-1 to make bus links andconnections among adjacent memory modules. In addition, a switch (seesymbol 29) may also be provided between the point of contact from memorymodule input terminal to bus and point of contact from memory moduleoutput terminal to bus. In FIG. 1, the aforementioned switches areindicated by the broken circles.

Moreover, the memory modules 14 are preferably provided not only with asingle input terminal and single output terminal, hut also one or moreother terminals (I/O terminals, etc.). For example, in Embodiments 2 or3 to be presented later, processing is implemented using I/O from threeor more terminals.

A plurality of buses 24-1, 24-2, 24-3, 24-4, . . . is provided betweenthe CPU module 12 and the memory modules 14. Accordingly, data and thelike can be exchanged among the memory modules by means of theaforementioned buses. In addition, a signal control line 25 is providedbetween the CPU 12 and the memory modules 14, so that instructionsissued by the CPU 12 are transmitted to all of the memory modules 14.

Moreover, a local bus 26 is provided between the CPU 12 and variousother constituent elements (e.g., the hard disk drive 16, input device18, etc.), so data and the like can also be exchanged among them also.The CPU 12 reads a program stored on the hard disk drive 16 or RAM orother storage devices (not shown) connected to the local bus 26, andfollows this program to execute the sending of instructions to thememory modules 14 and other exchanges of data, along with control of theswitches 28, 30 and the like. In addition, in accordance with theprogram, the CPU 12 accepts data in various formats stored in legacymemory 22, converts this formatted data to a series of data (array) thatcan be processed by the system consisting of the CPU 12, memory modules14 and bus 24, and stores this in the various memory modules 14.

FIG. 2 is a schematic block diagram showing a memory module 14 accordingto this embodiment. As shown in FIG. 2, the memory module 14 consists ofa clock buffer 32 that accepts clock and other synchronization signalsgiven by the CPU module 12, a RAM core 34 that stores data, a processor(MPU) 36 that recognizes the space ID and element numbers of data (to bedescribed later), and upon accepting an instruction or the like from theCPU 12, writes data to the RAM core 34 or reads data from the RAM corebased on the space ID and element number, and an I/O unit 38 thatreceives data from one of the buses and supplies it to the RAM core 34,and/or sends data from the RAM core 34 and sends it out on one of thebuses. In this embodiment, the memory module 14 is able to receiveinstructions from the CPU via the signal control line 25, respond tothese instructions and perform the reading of data from the RAM core 34,writing of data to the RAM core 34 or perform other stipulatedprocessing on data. In addition, data access to the RAM core 34, anddata input and data output via the I/O unit are executed based on aclock or other synchronization signal given by the clock buffer 32. Theprocessor (MPU) 36 of the aforementioned memory modules 14 preferablyconsist of a plurality of processing units and can execute a pluralityof processes in parallel.

As is clear from FIG. 1 and FIG. 2, in the present invention, thecomputer system 10 may be thought of as a shared memory type system. Inaddition, as described later, processing is executed in parallel by thevarious memory modules 14 by giving instructions to the memory modules14 via the signal control line 25. In addition, data output to the busand data input from the bus and the like are executed based onstipulated synchronization signals. Accordingly, this computer system 10may be considered to take the form of a SIMD system.

The computer system 10 having such a configuration is fundamentallyprovided with the multi-space memory, memory modules and reconfigurablebus recited in Japanese Patent Application No. H11-263793. Here followsa brief description of these.

(1) Multi-Space Memory

In this Specification, a “multi-space memory” refers to a memory whereinthe memory space is allocated such that it is accessed based on a spaceID and address. Thereby, even when a series of data is divided amongmany processors, each processor is able to separate and recognize itreliably.

In the conventional memory space, even if separate regions are allocatedfor each process, the allocation of memory space was not performed foreach series of variables (arrays, structures, etc.). Accordingly, such aconventional memory space is described in the following as a “singlememory space.” In a system with a single memory space, data access isperformed using only the address, so it was not possible to separate orrecognize a series of associated data. For this reason, even if parallelprocessing is actually possible, there are many cases in which thiscannot be determined. In addition, when a new series of data is storedin a certain single memory space, it was necessary to perform garbagecollection in order to secure a place to store the series of data inquestion.

In contrast, in the present invention, a space ID is introduced into thememory space, thereby applying the same ID to a series of data. Inaddition, each of the memory modules 14 recognizes the space ID for thedata kept in its own RAM core 34, and thereby each memory module 14 isable to determine whether or not it needs to operate by looking up thespace ID of the data currently being accessed. In addition, because eachmemory module 14 can keep all or some of a series of data associatedwith a space ID, it is possible to store a certain series of datadivided among a plurality of memory modules 14, and thereby garbagecollection becomes unnecessary.

(2) Memory Modules

In addition, in the present invention, each of the memory modules 14 hasa processor 36 that recognizes the individual element numbers of theseries of data that it keeps itself. Accordingly, upon accepting aninstruction from the CPU 12, the processor 36 is able to determinewhether the data to be accessed according to the instruction is keptwithin its own RAM core 34 or not and thereby determine whether accessis necessary or not. Moreover, each of the memory modules 14 is able todetermine from the range of subscripts in the array elements stored inits own RAM core 34 the range of the burden of implicit processing ininstruct ions under SIMD.

The memory modules 14 are able to reorder the storage order of elementsto be processed according to an instruction from the CPU 12, and sortthe elements stored within its own RAM core 34.

(3) Reconfigurable Bus

With the present invention, the CPU 12 is able to selectively turnon/off switches 28-1, 28-2, . . . and switches 30-1, 30-2, . . . , andthus specify the memory module 14 with which data is to be exchanged,thereby achieving pipeline processing. For example, as shown in FIG. 3,if data output from a certain memory module 14-i is to be given toanother memory module 14-j, and data output from this other memorymodule 14-j is to be transmitted to yet another memory module 14-k, thenthe CPU 12 sets the states of the various switches so that bus 24-m isallocated to memory modules 14-i and 14-j and bus 24-n is allocated tomemory modules 14-j and 14-k.

Moreover, this pipeline processing can be achieved not only in the caseof connections among single memory modules, but it can also be achievedby connections among a plurality of series of memory modules (memorymodule groups). Depending on the processing to be achieved, the variousmemory modules can be reconnected so that it is possible to performone-directional continuous transmission of stipulated types of data in astipulated order on each connection route, thereby schedulingcommunication so that nearly 100% of the capacity of the bus can beused. Thereby, the poor performance of interprocessor communicationwhich is the greatest problem of distributed memory type parallelprocessing systems can be solved.

[Multi-Space Memory]

We shall now give a more detailed description of the memory managementof various memory modules and memory access according to instructions ina computer system according to the present invention that uses amulti-space memory.

FIGS. 4A to 4C are diagrams used to describe the structure of a memorymodule 14 under a multi-space memory. As shown in FIG. 4A, a space IDcontrol table is provided in the RAM core 34 within the memory module14. Thereby, the processor 36 of the memory module 14 can determine thespace ID of the data kept by itself and other necessary information.

As shown in FIG. 4B, the space ID control table contains, for each groupof data it keeps, the space ID, the logical start address under CPUcontrol, the size of the region allocated to the data group, thephysical start address within RAM core 34, the total size of the seriesof data having the space ID in question, and access control flags thatcontrol access. The access control flags can be set to one of the threestates of read only (R), write only (W) or read/write enabled (RW).

When given a data group having a certain space ID, the processor 36 ofthe memory module 14 finds one or more regions in the RAM core 34 wherethe data group in question is to be stored and stores the data group insaid regions as is or divided into two or more parts. At this time, thelogical start address within the RAM core where the data is actuallystored and the allocated region size are stored in the space ID controltable together with the given space ID, logical start address, totalsize and access control flags. FIG. 4C is a diagram showing the datastored within the RAM core 34 according to the space ID control table ofFIG. 4B.

[Brief Discussion of Memory Access]

Here follows a description of accessing a memory module 14 having such aconstitution. As shown in FIGS. 5A to 5C, the CPU 12 first transmits thespace ID, logical address and required instruction (e.g., read or writedata) to all memory modules 14 via the signal control line 25. Inresponse, each of the memory modules 14 uses the space comparator 52provided in the processor 36 to compare the space ID against the spaceID's kept in its own space ID control table, and determines if the sameone is kept by itself. Also, the address comparator 54 performs the sametype of determination regarding the logical address. Next, if the datasubject to the instruction is determined to be kept within its own RAMcore 34, the processor 36 of the memory module 14 uses an addresscalculator 56 to look in the space ID control table to calculate thephysical address within RAM core 34 and identify the data subject toprocessing.

Once the data is identified in this manner, the processor 36 executesthe processing corresponding to the instruction given by the CPU 12(e.g., read or write data), and if necessary, transmits the data to theCPU 12 (see FIG. 5C).

[Sorting (Embodiment 1)]

Here follows a description of sorting by means of a computer system 10having such a configuration. Note that in the following description,each memory module is a memory module equipped with a processor and isthus referred to as a Processor Memory Module (PMM).

For ease in understanding, consider a case such as that shown in FIGS.6A to 6C, wherein each of four PMMs holds two elements (surnames). Asshown in FIG. 6A, a certain PMM (the first PMM 14-1) holds the surname“Smith” with an element subscript (record number) of “0” and the surname“Carter” with a subscript of “1.” The second PMM 14-2 holds the surname“Clinton” with a subscript of “2” and the surname “Johnson” with asubscript of “3.” Similarly, the third PMM 14-3 and fourth PMM 14-4 holdsurnames corresponding to the subscripts shown in FIG. 6A. The samespace ID is applied to the array consisting of these elements, and theprocessor 36 of each PMM uses its space ID control table to manage thesubscripts (record numbers) of the elements managed in its own RAM core34, along with the physical address where they are actually stored andthe like.

For example, consider the case wherein an instruction to sort the arrayhaving this space ID is given by the CPU 12 to the various PMMs 14-1through 14-4 via the signal control line 25. FIG. 7 is a flowchartshowing the procedure for sorting according to this embodiment. As shownin FIG. 7, when the CPU 12 issues an instruction (e.g., the instruction“sort the elements within an array having a certain space ID”) (Step700), in response to this instruction, in each PMM, the processor 36 ofeach PM receives the instruction given via the signal control line 25and interprets its content (Step 701), examines the “space ID” withinthe instruction (Step 702), and determines whether it pertains to thespace ID of data held by its own RAM core 34 (Step 703). If the resultof Step 703 is No, then processing ends. On the other hand, if theresult is Yes, the processor 36 performs various required checks such aschecking that the data group pertaining to the space ID in question isin the write-enabled state (Step 704). If an error results from thechecks (a “Yes” result in Step 705), the processor 36 reports the errorto the CPU 12 via the signal control line 25. On the other hand, ifthere is no error, the processor 36 executes the main body of thesorting process described below (Steps 707 and on).

First, each of the PMMs 14-1 through 14-4 executes a sort on its ownelements (Step 707). This sort actually accompanies the replacement ofelements within the various PMMs. More specifically, the processor 36uses Quicksort or another known sorting technique to sort the elementsheld in its own RAM core 34. FIG. 6B is a diagram showing the state inwhich the elements within the arrays of each PMM sorted. Note that asshown in FIG. 6D, the placement of the subscript (record number) foreach element is also changed.

Next, the processor 36 of each memory module 14 allocates a region(sequence number region) for placing the sequence numbers and gives aninitial value for each sequence number (Step 708). FIG. 6C is a diagramshowing the state of each PMM wherein the initial values of the sequencenumbers are given. In this manner, the sequence numbers are assignedamong the sorted elements within each module.

Next, the merging and assignment of sequence numbers among adjacentpairs is executed (Step 709). In Step 709, the CPU 12 first controlsswitches 28 and 30 on the bus 24 so that among the PMMs involved in asort, the input to one side of a certain pair is connected to the outputof the other side, and the output to that one side is connected to theinput of the other side. The aforementioned pair is preferably twoadjacent PMMs or if not adjacent, two PMMs that are at neighboringpositions. For example, in FIG. 1, if PMMs 14-1 through 14-4 areinvolved in a sort, PMMs 14-1 and 14-2 and PMMs 14-3 and 14-4 arepreferably taken as pairs. For example, as shown in FIG. 8, the CPU 12may control the switches 28 so that the output of PMM 14-1 and the inputof PMM 14-2 are connected to bus 24-1, the input of PMM 14-1 and theoutput of PMM 14-2 are connected to bus 24-2, and control the switches28 so that the output of PMM 14-3 and the input of PMM 14-4 areconnected to bus 24-1, the input of PMM 14-3 and the output of PMM 14-4are connected to bus 24-2. Moreover, the CPU 12 also turns off theswitches 30-5 and 30-6 on buses 24-1 and 24-2 placed between PMM 14-2and PMM 14-3. In FIG. 8, the black circles indicate the state ofcontinuity, while the white circles indicate the state of non-continuityand not being connected to the PMM. In addition, the remaining onesfollow the state of the other PMMs (not shown). Note that in the exampleof FIG. 8, one can understand that the bus can be utilized moreeffectively by dividing the buses 24-1 and 24-2 by turning switches 30-5and 30-6 off.

In this manner, as shown schematically in FIG. 9, the connections amongPMMs are defined by the CPU 12 and the main body of the sequence numberassignment is executed among pairs of PMMs. FIGS. 10 through 12 arediagrams that schematically show the sequential numbering of arraysshown in FIG. 6. FIGS. 13A-13C are flowcharts that show more generalsequential numbering among PMM pairs.

FIGS. 10A through 12C illustrate only the processing of PMM 14-1 and PMM14-2, but the processing of PMM 14-3 and PMM 14-4 are also executed inparallel. Note that in the processing, the one that first gives data toanother PMM is called the former PMM and the one that receives it (theother PMM) is called the latter PMM. The former PMM can also be calledthe presentation PMM because it presents the elements or sequencenumbers, and on the other hand, the latter PMM can also be called thedetermination PMM because it determines the presented sequence numbers.Either one of the pair can be the former PMM. In this example, forconvenience, the PMM 14-1 is made the former PMM and PMM 14-2 is madethe latter PMM.

First, in the former PMM, a pointer that indicates the processingposition (hereinafter referred to as the “PUT pointer”) is placed at theinitial position (beginning of the sorted array portion or the “0^(th)”position). On the other hand, in the latter PMM, as described below, theelement received from the former PMM and a pointer that first indicatesthe position to be compared and the like (hereinafter referred to as the“comparison pointer”) are placed at the initial position (beginning ofthe sorted array portion or the “0^(th)” position). (See FIG. 10A andSteps 1301 and 1311 of FIG. 13A and FIG. 13B.) In this embodiment, thecomparison pointer used in the latter PMM is a structural array of theform (X, Y, Z). Here, X indicates the starting position to be compared(namely, the starting position of the elements yet to be compared;hereinafter referred to as the “unprocessed position”), Y indicates thetotal number of elements received from the former PMM (hereinafterreferred to as the “forward insertion number” depending on the case) andZ is a proposed sequence number for the element given by the former PMMin a virtual array obtained upon merging the former PMM and latter PMM(called a “virtual sequence number” depending on the case).

Next, the initial data transmission is executed by the processor of theformer PMM. In this data transmission, the element at the positionindicated by the PUT pointer is transmitted to the latter PMM via thebus (see FIG. 10B and Steps 1303 and 1312). Note that in the branch inStep 1302, the result is always Yes in processing among two PMMs, butthis will be described later. In the first data transmission, theelement “Carter” is transmitted to the latter PMM. The latter PMM findsthe position at which the transmitted element “Carter” is to be insertedin the portion of the array stored in the latter PMM (Step 1313). Thisneed not be the actual insertion of a value, but rather it is sufficientto find the position at which the element is to be inserted. In thisembodiment, the elements stored in the array portions are actuallyplaced in the sorted state. Accordingly, the insertion position can befound by means of the bisection method or other high-speed searchtechniques. By finding the insertion position, it is possible toidentify the range of elements whose sequence is not determined that areelements positioned before the insertion position (hereinafter referredto as “Range 1”). Note that in this embodiment, there is a conventionthat in the case that the element is the same, the sequence of thelatter PMM lakes priority. Accordingly, in the event that the element“Carter” transmitted from the former PMM is present in the latter PMM,the sequence when stored in the latter PMM takes precedence (namely, hasa smaller sequence number).

In this example, one can see that the element “Carter” transmitted fromthe former PMM is positioned before the element “Carter” within theportion of the array managed by the latter PMM, and thus one can seethat elements belonging to the Range “1” are not present (see FIG. 10Cand Yes in Step 1314). Then, the processor of the latter PMM sets thesequence number of the transmitted element “Carter” to “0 (namely thebeginning)” and returns it to the former PMM (Step 1315). Next, theprocessor of the latter PMM increments the forward insertion number to“1” and also increments the virtual sequence number to “1” (Step 1316).This is because, since the number of elements transmitted from theformer PMM is increased by one, it is necessary to increment the forwardinsertion number and the sequence number of the next element must beincremented must be incremented for at least the one given this time (inthis case, “0”).

When the sequence number (insertion position of the element is given bythe latter PMM (Step 1332), the processor of the former PMM stores thesequence number given as the sequence number of the element in question(Step 1334), and then increments the PUT pointer (see FIG. 11A and Step1335). In this manner, the sequence of elements within the former PMM isdetermined.

Next, the processor of the former PMM transmits the element “Smith” atthe position indicated by the PUT pointer to the latter PMM via a bus(see FIG. 11B and Step 1303). In the same manner as when the element“Carter” was transmitted previously, the latter PMM finds the positionwhere the transmitted element “Smith” is to be inserted (Step 1313). Onecan see that the element “Smith” is positioned after the element“Monroe” within the portion of the array managed by the latter PMM (seeFIG. 11C and Yes in Step 1314). Thereby, in the portion of the arraymanaged by the latter PMM, it is possible to determine the number of theelement “Monroe” and the elements positioned before it, and the sequenceof the various elements. More specifically, the processor of the latterPMM determines the sequence of the aforementioned elements by thefollowing procedure.

First, the forward insertion number “Y” is added to each of the sequencenumbers pertaining to the elements contained within Range “1” (Step1317). Thereby, the sequence of elements contained within Range “1” isdetermined. In the aforementioned example, the sequence number of theelement “Carter” becomes “0+1=1” and the sequence number of the element“Monroe” becomes “1+1=2.” Next, the sequence number of the last elementwithin the elements contained in Range 1 is substituted into the virtualnumber and also (Step 1318), the unprocessed position is changed to theposition of the next element after the last element in Range 1 (Step1319). In the aforementioned example, the sequence number “2” of theelement “Monroe” is given in Z of the comparison pointer (structurearray), and the unprocessed position is changed from “0” to “2.”Thereby, the structure array becomes (2, 1, 2).

After this process, the forward insertion number “Y” and virtualsequence number “Z” within the structure array are incremented (Step1320). Thereby, the structure array becomes (2, 2, 3) (see FIG. 11D).The virtual sequence number obtained in Step 1320 becomes the sequencenumber of the element obtained in Step 1312 (in the aforementionedexample, “Smith”), and the processor of the latter PMM transmits thesequence number in question (in the aforementioned example, “3”) to thelatter PMM (Step 1321). After this process, the virtual sequence numberis incremented further (Step 1322). This is because the sequence numberof the next element becomes at least one larger than the sequence numbergiven this time.

The former PMM stores the received sequence number as the sequencenumber of the element in question and increments the PUT pointer. Inthis manner, the sequence number in the former PMM is determined.

In the event that no unprocessed elements are present in the former PMM(to wit, a sequence number is established for all elements and noelement is placed at the position of the PUT pointer), the processor ofthe former PMM transmits a value that indicates the end to the latterPMM (see Step 1306). Here, the “value that indicates the end” is a valuegreater than the value that indicates the element at the end of thearray. In response to the aforementioned value that indicates the end,the latter PMM executes a process nearly identical to this process(Steps 1312-1322 of FIG. 13B). In the aforementioned example, regardlessof the receipt of the value indicating the end, no elements contained inRange “1” are present, so processing reaches Step 1323 via Steps 1315and 1316 and ends (see FIG. 12B).

In the former PMM, by sending the value that indicates the end (see Step1316) and by determining the sequence numbers of all elements (Yes inStep 1336), processing ends.

Merging is performed between PMM 14-3 and PMM 14-4 by a proceduresimilar to the aforementioned process, and thus the sequence numbers ofeach element are determined as shown in FIG. 12C.

When the sequence numbers of each element are determined in the twoPMMs, the CPU 12 changes the positions of the switches to connect twoPMM groups each consisting of two PMMs. FIG. 14A and FIG. 14B arediagrams that show one example of the connection of two PMM groups withthe PMMs shown in FIG. 8. In FIG. 14A, PMMs 14-1 and 14-2 constitute thefirst PMM group and PMMs 14-3 and 14-4 constitute the second PMM group.CPU 12 controls the switches 28 and 30 so that the outputs of PMMs 14-1and 14-2 are connected to the inputs of PMM group 14-3 and the output ofPMM 14-3 is connected to the input of PMM 14-4 and the output of PMM14-4 is connected to the input of PMMs 14-1 and 14-2 (see Step 709 ofFIG. 7). Alternately, as shown in FIG. 14B, the switches can becontrolled so that the outputs of PMMs 14-1 and 14-2 are connected toPMMs 14-3 and 14-4.

FIGS. 15A and 15B are diagrams that schematically represent FIGS. 14Aand 14B, respectively. As will be made clear later, in FIG. 15A, thedata given from PMM 14-4 to PMMs 14-1 and 14-2 (symbol (1) in thefigure) indicates the sequence number, while the data given from PMMs14-1 and 14-2 to PMM 14-3 (symbol (2) in the figure) indicates theelement, and the data given from PMM 14-3 to PMM 14-4 (symbol (3) in thefigure) indicates the element and the virtual sequence number calculatedby PMM 14-3. In addition, in FIG. 15B also, the data (1) and (2)exchanged among the PMMs are the same as those in FIG. 15A, and on theother hand, the data transferred from PMM 14-3 to PMM 14-4 (see symbol(3)) indicates the virtual sequence number calculated by PMM 14-3.

Here follows a description of the process of merging two PMM groups andthe process of determining the sequence numbers of an array from theportion of the array in two paired PMMs and the sequence numbers ofelements contained therein, as shown in the aforementioned FIGS. 12A to12C (see Step 709 of FIG. 7). Note that in the following description,the processes executed in each PMM are described according to the busconnection state indicated in FIG. 14B and FIG. 15B.

First, in the PMM 14-1 and PMM 14-2 respectively (hereinafter referredto as the “former PMM group”), the PUT pointer is placed at the initialposition (Step 1301). Note that in the subsequent process, each of thePMMs that make up the former PMM group moves the PUT pointer accordingto the sending of elements that itself controls. On the other hand, eachof the latter PMMs places the comparison pointer at the initial positionat the time of initialization of its structure array (Step 1302). Then,in each of the PMMs that make up the former PMM group, currently, thePMMs that make up the former PMM group determine the sequence number ofthe element which was sent.

Note that in the flowchart, both the send pointer used when sending andthe receive pointer are used as the PUT pointer, but fundamentally, themovement of these send and receive pointers sandwiches the processingtime in the latter PMM group, but it is performed with only a slighttime difference. For example, as described later, when the send pointeris incremented in a certain PMM (sec Step 1304), the PMM in questionincrements the receive pointer in the receive process also (see Step1335).

The PMMs that make up the former PMM determine if the element inquestion is controlled by itself based on the sequence number of theelement subject to processing (Step 1302). It the result of this Step1302 is Yes, the element pointed to by the PUT pointer is transmitted toPMMs 14-3 and 14-4 via bus 24 (see Step 1302 of FIG. 13A and FIG. 16A).In the aforementioned example, the element “Carter” with a sequencenumber of “0” is transmitted from PMM 14-1 to PMM 14-3 and PMM 14-4. Bythis process the position of the PUT pointer is moved in PMM 14-1 (Step1304).

PMM 14-3 and PMM 14-4 each receive elements (Step 1312), find theposition at which those elements are to be inserted (Step 1313) anddetermine whether any elements belonging to Range “1” are present (Step1314). For the aforementioned element “Carter,” the result of Step 1314is No.

Thereby, in PMM 14-3, the virtual sequence number of the element“Carter” becomes “0” so this value is transmitted to PMM 14-4. Thevirtual sequence number of the element “Carter” becomes “0” in PMM 14-4also. Thus, the processor of PMM 14-4 returns “MAX(0, 0)=0” as thesequence number of the element “Carter” to the former PMM group via thebus (see FIG. 16B and Step 1315). Then, in PMMs 14-3 and 14-4, theforward insertion number (Y) and virtual sequence number (Z) within thestructure array are each incremented (Step 1316). In the aforementionedexample, the structure arrays of each thus become (0, 1, 1), (0, 1, 1).

When a sequence number is given from the latter PMM group (Step 1331),the PMMs that make up the latter PMM group determines whether theelement currently being processed (e.g., the element “Carter”) is onethat it controls itself (Step 1333). In the event that the sequencenumber of the element “Carter” is transmitted, PMM 14-1 finds that Yesis the result of the aforementioned Step 1333, and replaces the sequencenumber corresponding to the element at that position with that given bythe latter PMM group (see FIG. 16A and Step 1334).

In the same manner, the latter PMM group transmits the element given thenext sequence number to the latter PMM. In the aforementioned example,the element “Carter” is transmitted from PMM 14-2 (see FIG. 17A), andthose of each of the latter PMM group with a higher virtual sequencenumber “MAX(1, 1)=1” are transmitted to the former PMM group as thesequence number of the element “Carter” in question (see FIG. 17B). Inaddition, in the PMMs 14-3 and 14-4 that make up the latter PMM group,the structure arrays become (0, 2, 2) and (0, 2, 2), respectively (seeFIG. 17B).

Moreover, the former PMM group transmits the element given the nextsequence number to the latter PMM. In the aforementioned example, theelement “Monroe” is transmitted from PMM 14-2 (see FIG. 18A). In PMM14-3, the element “Monroe” is determined to be behind the element“Kennedy” controlled by the PMM 14-3 in question (see Step 1313).Accordingly, in PMM 14-3, since the element “Gore” and the element“Kennedy” belong to the Range “1,” the forward insertion number “Y (=2)”is added to the sequence numbers of the element “Gore” and the element“Kennedy,” respectively. Thereby, the sequence number of the element“Gore” is determined to be “0+2=2” and the sequence number of theelement “Kennedy” is determined to be “2+2=4” (see Step 1317). Then, theprocessor of PMM 14-3 sets the virtual sequence number Z of thestructure array (current value is (0, 2, 2)) to the sequence number “4”of the end element within the Range “1” (see Step 1318) and advances theunprocessed position (namely, changes the value of X from “0” to “2”)(see Step 1319). Furthermore, the processor of PMM 14-3 increments theforward insertion number “Y” and virtual sequence number “Z” of thestructure array (current value is (2, 2, 4)) (see Step 1321). Thereby,the structure array becomes (2, 3, 5). The virtual sequence number “Z(=5)” in PMM 14-3 is transmitted to PMM 14-4 via the bus. Thereafter,the processor of PMM 14-3 increments the virtual sequence number “Z” ofthe structure array (sec Step 1322). In the aforementioned example, thestructure array becomes (2, 3, 6) by performing Step 1322.

On the other hand, in PMM 14-4, the element “Monroe” is determined to bepositioned between the elements “Johnson” and “Wilson” that the PMM 14-4in question controls (see Step 1313). Accordingly, in PMM 14-4, theelement “Johnson” belongs to the Range “1” so the forward insertionnumber “Y (=2)” is added to the sequence number of the element “Johnson”and thus the sequence number of the element “Johnson” is determined tobe “1+2=3” (see Step 1317). Then, the processor of PMM 14-4 sets thevirtual sequence number “Z” of the structure array (current value is (0,2, 2)) to the sequence number “3” of the end element within the Range“1” (see Step 1318) and advances the unprocessed position (namely,changes the value of “X” from “0” to “1”) (see Step 1319). Furthermore,the processor of PMM 14-4 increments the forward insertion number “Y”and virtual sequence number “Z” of the structure array (current value is(1, 2, 3)) (see Step 1321). Thereby, the structure array becomes (1, 3,4).

Thereafter, PMM 14-4 compares the virtual sequence number “Z (=5)” givenfrom the PMM 14-3 against the virtual sequence number “Z (=4)”calculated by itself, finds the larger value “MAX(5, 4)=5” and transmitsthis to the former PMM group as the sequence of the transmitted element“Monroe.” Thereby, in the former PMM group (more specifically, in thePMM 14-4 that had sent the element “Monroe”), the sequence number of theelement in question is determined to be “5.” Note that in PMM 14-4 also,after Step 1321, the virtual sequence number “Z” within the structurearray is incremented (see Step 1322). In the aforementioned example, thestructure array becomes (1, 3, 5).

The element “Smith” is sent from the former PMM group in the same manner(FIG. 19A), but the process in this case is also executed according toFIGS. 13A-13C. To describe this again briefly, the PMM 14-3 thatreceived the element “Smith” has no element belonging to the Range “1”present ahead of the insertion position of the element “Smith” so PMM14-3 transmits the virtual sequence number “Z (=6)” within its structurearray to PMM 14-4. The PMM 14-4 also has no element belonging to theRange “1” present ahead of the insertion position of the element “Smith”so it compares the virtual sequence number “Z (=5)” within its structurearray against the virtual sequence number “Z (=6)” thus transmitted,finds the larger value (MAX(6, 5)=6) and transmits this to the formerPMM group as the sequence of the element “Smith” (see FIG. 19B and Step1315). In the former PMM, the PMM 14-1 that sent the element “Smith”rewrites the sequence number corresponding to the element “Smith” withthe received sequence number (=6). Note that in PMM 14-3, by passingthrough Step 1316, its structure array becomes (2, 4, 7) and on theother hand in PMM 14-4, by passing through Step 1316, its structurearray becomes (1, 4, 6).

In this manner, when the sending of all elements in the former PMM groupends, one of the PMMs that make up the former PMM group transmits avalue indicating the end to the latter PMM group (see Step 1306). Eachof the PMMs that make up the latter PMM group receives this and executesthe processing of Steps 1312 through 1323. In the aforementionedexample, the element “Wilson” for which a sequence is not determined ispresent in PMM 14-4. For this reason, in PMM 14-4 when the result ofStep 1314 is Yes, the forward insertion number “Y” is added to thesequence number of the element “Wilson” belonging to Range “1” to give“3+4=7” and the number “7” thus obtained is set as the sequence numberof the element “Wilson.” After passing through this process, each of thePMMs that make up the latter PMM group obtain the result Yes in Step1323, and the process ends in the latter PMM group also.

In the aforementioned example, the elements within the array are storedin four PMMs, but even in the event in which elements are stored withinarrays in a larger number of PMMs, it is sufficient to prepareadditional pairs of PMM groups each consisting of four PMMs and executea similar process among these pairs. Consider the case such as thatshown in FIG. 20, for example, wherein the elements within a certainarray are stored within 1024 PMMs. In this case, first PMM 1 and PMM 2,PMM 3 and PMM 4, PMM 5 and PMM 6, . . . , PMM 1023 and PMM 1024 arelinked to each other (see the solid lines among PMMs), and the sequencenumbers of elements are determined among these two PMMs, and then a pairof PMM groups consisting of PMM 1 and PMM 2 taken as the former PMMgroup and PMM 3 and PMM 4 taken as the latter PMM group, a pair of PMMgroups consisting of PMM 5 and PMM 6 taken as the former PMM group andPMM 7 and PMM 8 (not shown) taken as the latter PMM group, . . . , and apair of PMM groups consisting of PMM 1021 and PMM 1022 (not shown) takenas the former PMM group and PMM 1023 and PMM 1024 taken as the latterPMM group are formed and the pairs are linked to each other (see thebroken lines), and the sequence numbers of elements are determined amongthe PMM groups that make up these pairs. Thereafter, pairs of PMM groupsconsisting of four PMMs as the former PMM group and the subsequent fourPMMs as the latter PMM group are formed (sec the dashed-dotted lines),and then pairs of PMM groups consisting of eight PMMs as the former PMMgroup and the subsequent eight PMMs as the latter PMM group are formed(sec the dotted lines) are formed, and in this manner, pairs of PMMgroups each consisting of 2^(n) PMM groups are sequentially formed, andthen the sequence numbers of elements are determined among them.Ultimately, the sequence numbers of all elements within the 1024 PMMscan be determined by determining the sequence numbers of elements withina pair of PMM groups consisting of a former PMM group of 512 PMMs and alatter PMM group of 512 PMMs.

In this manner, by forming pairs of PMM groups each consisting of 2^(n)PMMs and sequentially determining the sequence numbers of elementsstored in each PMM of the PMM groups that make up the pairs (see Steps709 and 710 of FIG. 7), ultimately the sequence numbers of all elementsare determined (Yes results in Step 710), and then, if necessary, theprocess of reforming the arrays according to the aforementionedsequential numbering is executed (Step 711). This process is notmandatory, but by generating an array wherein the elements are placedaccording to the sequence number, information processing to be executedlater can be implemented at high speed.

More specifically, the CPU 12 controls the switches 28 and 30 so thatthe inputs and outputs of each PMM are connected by a certain bus. FIG.21 is a schematic diagram showing the case of connections among fourPMMs. Next, the processors of PMMs 14-1 through 14-4 release theelements and sequence numbers upon the bus according to the sequencenumbers determined. Each processor monitors the elements and theirsequence numbers released upon the bus, gets elements that have the samesequence number as the element subscripts (record numbers) that hadoriginally been managed by its own RAM core, and stores them in theappropriate regions of the RAM core. For example, it is sufficient forthe PMM that had originally stored the elements with subscripts (recordnumbers) “0” and “1” in its own RAM core (e.g., see PMM 14-1 of FIG. 10)to get the elements marked with the sequence numbers “0” and “1” andstore them. By doing so, it is possible for each PMM to manage the arrayactually sorted. Note that in this manner, the processor of the PMMcreates the space ID control table at the time of creating a sortedarray also.

Alternately, as shown in FIG. 22, it is sufficient to provide other PMMs(PMM 14-5 through PMM 14-8) to manage the sorted array, so that each ofthe other PMMs monitors the sequentially output elements and theirsequence numbers, gets the elements to be stored by itself according tothe sequence numbers and stores them in the RAM core of each PMM.

For example, consider the case of using the aforementioned presentinvention to provide 1024 PMMs, store approximately 1 million pieces ofdata (elements) in each PMM, and perform a sort of this data. In thiscase, the sort was completed in the following amount of time. Here, weare assuming that each of the buses connecting the PMMs has a datacapacity of 6.4 GB/s, all of the PMMs operate in parallel during theprocessing (namely, no PMM that is not executing a process is present),and all associated PMMs can operate cooperatively and simultaneously. Inaddition, the sorting of approximately 1 million pieces of data(elements) in each PMM is assumed to be complete in 2.5 seconds. In thiscase, one can see that sorting the approximately 1 billion elementscontained within the 1024 PMMs would require only roughly 4 seconds.

By means of this embodiment, the PMMs are initially divided into pairsof two PMMs, but they are subsequently divided into PMM groups whereeach group is made up of 2^(n) PMMs, and then the sequence numbers aredetermined among each pair. In addition, by using switches or the liketo regulate the buses used for each pair, the determination of sequencenumbers among each pair can be executed in parallel. Moreover, byrepeating the procedure of transmitting elements from the former PMMgroup to the latter PMM group, establishing sequence numbers accordingto values within the structure array in the later PMM group, it ispossible to establish the sequence numbers in all pairs. Accordingly,the processing can be executed in an extremely parallel manner withoutgenerating any PMMs that are not executing any processing (so-called“idle” PMMs), and also it is possible to reduce the amount of datatransferred using the bus. This permits the sorting speed to be maderemarkably fast.

Note that in the aforementioned Embodiment 1, as shown in FIG. 14B andFIG. 15B, the sorting is implemented by connecting PMMs and assigningsequence numbers to the elements among them, but the PMMs may also beconnected as shown in FIG. 14A and FIG. 15A. In this case, theprocessing of the latter PMM group in FIG. 13B (Step 1312 through Step1323) is not performed in parallel, but once a virtual sequence numberis obtained in a certain PMM, the element subject to processing andvirtual sequence number in question are transmitted to the adjacent PMM,and the processing of Steps 1312 through 1323 is performed in this PMM.Accordingly, as the number of PMMs that make up the latter PMM groupbecomes larger, there are cases in which this leads to a commensuratedelay in processing.

[Other Sorting (Embodiment 2)]

Here follows a description of Embodiment 2 of the present invention. Inthe aforementioned Embodiment 1, all of the elements (elements withinthe former PMM group) are transmitted to the latter PMM group. However,as the array becomes larger, a large number of duplicate values mayappear. With the technique according to the aforementioned Embodiment 1,elements that take the same value are sent on the bus many times.Depending on the case, one may think that repeatedly sending elementshaving the same value would be wasteful. Thus, in Embodiment 2, thenumber of elements within the PMM group is counted in advance, and bysending the number of elements together with that element to the latterPMM group, the repeated sending of duplicate elements over the bus isprevented.

For example, consider the case in which the sorting of four pairs ofPMMs is complete and these pairs are connected to perform the sorting ofeight PMMs. In this case, as shown in FIG. 23, it is preferable to beable to use a bus used to perform the merging and sorting of eight PMMs(the bus positioned below the PMM in FIG. 23; see symbols 2301 through2303) and exchange data among the PMMs. Here follows a description ofthe calculation of the redundancy of values in PMM 14-1 through PMM 14-4(hereinafter, for convenience, “PMM 14-1” through “PMM 14-4” arereferred to as “PMM 1” through “PMM 4” respectively) in the connectionmode shown in FIG. 23. Here, the bus (see symbol 2304) that connects theinput/output terminals (I/O) of PMM 1 through PMM 4 is called the firstbus, while the bus (see symbol 2305) that connects the otherinput/output terminals (I/O) of PMM 1 through PMM 4 is called the secondbus. The first bus is used for exchanging information for the PMM groupmade up of PMM 1 through PMM 4, while the second bus is used for givingthe values and their redundancy to the various PMMs.

Note that in the following description, as shown in FIG. 25, theredundancy of those to which sequence numbers are attached to eachelement is calculated in the array within PMM 1 through PMM 4. To wit,it is sufficient to calculate the redundancy for only the former PMMgroup. FIG. 24 is a flowchart showing the process of calculating theredundancy in the PMM group. Each of PMM 1 through PMM 4 first executesvarious initialization processes (Step 2401). Here, each PMM is providedwith a sequence-number counter that indicates the sequence number of thevalue (element) subject to processing, an identical-value counter thatindicates how redundantly a certain value (element) is present, aprevious-value storage register that holds the previous value (element)subject to processing, and the sequence-number counter andidentical-value counter are given an initial value of “0” as theirvalues (see FIG. 25). Note that initially, the previous-value storageregister holds no value.

Next, each PMM refers to the sequence-number counter to determine thesequence number of the element subject to processing, and determineswhether the element to which this sequence number is applied is one thatit manages itself (Step 2403). In the aforementioned example, the valueof the sequence-number counter is initially “0” so PMM 3 determines thatan element that it manages itself is subject to processing (Yes in Step2403). Note that the next Steps 2404-2405 are ignored in the initialprocessing (namely the processing of the element with a sequence numberof “0”). PMM 3 determines how many elements identical to the elementwith the sequence number of “0” (in this case, “Carter”) are presentwithin itself (namely, how many elements equal to “Carter” does PMM 3manage), and sends to the first bus the element “Carter” and the localPMM internal count, which indicates how many of these elements it has(Step 2406). The other PMMs (PMM 1, PMM 2 and PMM 4) obtain a result ofNo in Step 2403 and thus advance to Step 2407.

Each PMM receives data given via the first bus and based on the localPMM internal count, adds the PMM internal count to the value of thesequence-number counter (Step 2408). In the aforementioned example, thevalue of the sequence-number counter becomes “0+1=1.” Next, adetermination is made as to whether or not the given value is differentfrom that in the previous-value storage register (Step 2409), and if thetwo are identical, the local PMM internal count is added to the value ofthe identical-value counter (Step 2410), and on the other hand if it isa new value, the replacement process to be described later is executed(Step 2411). Note that in the initial iteration, the previous-valuestorage register has no value, so the aforementioned Step 2409 isomitted and the element is stored in the previous-value storage registerand also the identical-value counter is incremented. Accordingly, in theaforementioned example, each PMM stores the received element “Carter” inthe previous-value storage register and also the identical-value counteris set to “0+1=1” (see FIG. 26).

The processing of these Steps 2401 through 2411 is repeated and when theprocessing of the last element is complete, Yes results in Step 2401 soprocessing advances to Step 2412.

In the aforementioned example, when the processing of the first Steps2401 through 2411 is complete, each PMM refers to the value of thesequence-number counter and confirms that the value is “1.” Thereby thePMM 4 knows that it manages the element with the sequence number “1.” Inaddition, the PMM 4 compares the value of the previous-value storageregister (the element “Carter”) with the element “Carter” which has thesequence number “1” (Step 2404), and there is no change in the value soit sends the element “Carter” and the local PMM internal count “1” overthe first bus (Step 2405). As shown in FIG. 27, the PMMs that receivedata via the first bus increment (1+1=2) the sequence-number counter(Step 2408), and since the value stored in the previous-value storageregister is identical to the received element, they increment (1+1=2)the identical-value counter (Step 2410).

Thereafter, the processing of the element with sequence number “2” isexecuted in each PMM. In the processing of the element with sequencenumber “2,” PMM 1 holds an element, so PMM 1 compares the element“Clinton” against the element “Carter” stored in the previous-valuestorage register. Here, there is a change in the value (Yes in Step2404) so PMM 1 sends over the second bus the content of theprevious-value storage register (the element “Carter”) and the value “2”of the identical-value counter (Step 2405). This content of the registerand the counter value are given to the various PMMs. As described later,when the redundancy of a certain element (in this case the element“Carter”) is calculated, the sorting of the element in question (seeFIGS. 31A through 31C). Accordingly, the element and its redundancy maybe held in each PMM until the sorting of the element in question iscomplete.

In addition, the element “Clinton” and the local PMM internal count “1”are given to the first bus (Step 2406).

Based on the data given via the first bus, the PMMs increment (2+1=3)the sequence-number counter (Step 2408). In addition, the value “Carter”of the previous-value storage register is different from the transmittedelement “Clinton” (Yes in Step 2409) so the PMMs replace (update) thevalue of the previous-value storage register and also replace the valueof the identical-value counter to the local PMM internal count given viathe first bus (see Step 2411 and FIG. 28A).

The same process is performed on the elements with other sequencenumbers. For example, for sequence number “3” PMM 3 sends the element“Clinton” over the first bus according to Steps 2404 and 2406 andincrements the various counters according to Steps 2407, 2408, 2409 and2410 (see FIG. 28B). In addition, for sequence number “4” PMM 1 sendsthe element “Clinton” and the value “2” of the identical-value counterover the second bus according to Steps 2404, 2405 and 2406 andincrements the various counters according to Steps 2407, 2408, 2409 and2411 (see FIG. 29A).

In the processing of sequence number “5,” there are two “Johnson”elements that PMM 2 manages, so it sends the element “Johnson” and thelocal-PMM internal count “2” over the first bus. Accordingly “2” isadded to the value of the sequence-number counter and identical-valuecounter (see FIG. 29B). In addition, by means of this process, the valueof the sequence-number counter changes from “S” to “7” so note that thesequence number of the next element subject to processing becomes not“6” but “7.” When the processing of the last element with the sequencenumber of “7” (see FIG. 30A) is complete, Yes results in Step 2401.Then, the beginning PMM (PMM 1 in the aforementioned example) sends,over the second bus, the element “Johnson” and the value “4” of theidentical-value counter (Step 2413) and sends, over the second bus, datathat indicates that the processing has ended (Step 2414). Each PMM isgiven via the second bus each element and a count that indicates thenumber of elements, and these are used for sorting. Note that in theaforementioned example, the beginning PMM is constituted such that itexecutes Steps 2413 and 2414, but this is not a limitation, as it issufficient for the PMM to stipulate in advance the last element or thelike, and data that indicates the end.

As described above, by obtaining the numbers of various elements presentwithin a certain PMM group, at the time of merging a PMM group withanother PMM group and sorting these elements, there is no need to sendduplicate elements.

FIGS. 31A-31C are flowcharts showing sorting with the sending ofredundant elements omitted. FIGS. 31A-31C are identical to FIGS. 13A-13Cwith certain exceptions, so steps with the same last two digits areroughly corresponding processes. In addition, the steps in FIGS. 31A-31Cthat have double lines around them are newly added steps or steps thatare slightly different from the corresponding step in FIGS. 13A-13C. Inthis process, in the former PMM group, the PMM that manages the elementsubject to processing (namely, the element pointed to by the sendpointer) sends to the latter PMM group that element together with theredundancy (number present) “N” of that element in the former PMM group(see Steps 3103 and 3103-2). In the example shown in FIG. 25 throughFIG. 30B, for example, when the element “Carter” is sent from the formerPMM group made up of PMM 1 through PMM 4 to the latter PMM group, theelement “Carter” is transmitted along with the redundancy “2” of theelement “Carter” in the former PMM group. In addition, in the sendprocess of the former PMM group the PMM that outputs the element and itsredundancy moves the send pointer after that output by the number of theelements in question that it manages itself (Step 3104). For example, asshown in FIG. 28A, the redundancy of the element “Carter” is “2” andthese are managed one each in PMM 3 and PMM 4. Accordingly, the positionof the send pointer is moved down one each in PMM 3 and PMM 4. Note thatthe sum of movement of the send pointers in the PMMs is equal to theredundancy “N” of the element in question.

On the other hand, the PMMs that make up the latter PMM group thatreceived the element and its redundancy add the redundancy “N” to boththe forward insertion number and virtual sequence number as shown inStep 3116 and Step 3120 of FIG. 31B. This corresponds to the case inwhich there are “N” elements (with smaller sequence numbers) positionedin front of itself.

Moreover, in the receive process of the PMMs that make up the latter PMMgroup, the elements (data subject to comparison) sent in the sendprocess of the former PMMs and the sequence number sent in theprocessing by the latter PMMs are used to calculate the difference “M”between the received sequence number and the sequence number at the timeof sending of data subject to comparison (Step 3132-2). This difference“M” indicates the number of elements (given sequence numbers smallerthan the element in question) that are positioned before the elementsubject to comparison. Accordingly, the PMMs that make up the latter PMMgroup identify elements within the elements managed by it itself thatare identical to the element subject to the comparison in question (Step3132-3), and if present, add “M” to the sequence number of each of theseelements (Step 3134). After Step 3134, the PMM moves the receive pointerby the number of the elements in question (Step 3135). This process isroughly identical to Step 3104.

Here follows a description of parallelism in the calculation of theredundancy shown in FIG. 24 and in the sorting shown in FIGS. 31A-31C(sometimes called the “sort itself” depending on the situation). Asshown in FIG. 23, in this embodiment, the communication among PMMsinvolved in the counting of the redundancy is performed using buses 2304and 2305, while the communication among PMMs involved in the executionof the sort itself is performed using buses 2301, 2302, 2303 and thelike. To this end, if parallel processing is possible in the PMM, thecounting of redundancy and the sort itself can be executed in parallel.In this case, when the calculation of the redundancy of a certainelement in the former PMM group (e.g., as shown in FIG. 28A), theelement “Carter” and its redundancy “2” are sent over the second bus andwhen received by the PMMs (PMM 1 through PMM 4) that make up the formerPMM group, the process shown in FIGS. 31A-31C can be executed on theelement for which a redundancy is calculated. To wit, in response to thecalculation of the redundancy of a certain element, it is possible toexecute the processing of Steps 3102-3104, Steps 3112-3122 and Steps3132-3135 on the element in question. In addition, among the processingshown in the aforementioned FIGS. 31A-31C, a certain element and itsredundancy can be deleted together with the completion of thoseprocesses regarding the element in question. Accordingly, in each of thePMMs that make up the former PMM group, not all of the data pertainingto the element and its redundancy (the amount of which becomes larger asthe number of different elements increases) need be held.

In this manner, in Embodiment 2, the latter PMM group calculates theredundancy and sends the element and its redundancy to the latter PMMgroup. Accordingly, the former PMM group must send the same element tothe latter PMM group redundantly. In cases in which the number ofredundant identical elements is large (e.g., when an element indicatesthe sex of a person, or the age of a person, etc.), it is possible toreduce the number of times the sort itself is processed, so the sortingcan be achieved at even higher speed.

[Compiling (Embodiment 3)]

Here follows a description of Embodiment 3 of the present invention. InEmbodiment 3, based on an array consisting of elements placed withineach PMM, records, a value list without duplicate elements, and an arrayof pointers for specifying the value list from the record. In thisspecification, this process is called compiling.

For example, when the elements of a certain array are divided among fourPMMs (PMM 1 through PMM 4), it is sufficient to connect the PMMs asshown in FIG. 32. As shown in FIG. 32, the input/output pins (I/O) ofPMM 1 through PMM 4 are connected by the first bus (see symbol 3201) andon the other hand, the output pins (I) of PMM 1 through PMM 4 and theinput pins (I) of another PMM “k” are connected to the second bus (secsymbol 3202).

The first bus is used for exchanging information with the PMM group madeup of PMM 1 through PMM 4, while the second bus is used for giving theelements and their redundancy to another PMM “k.” In this embodiment,based on the aforementioned element and its redundancy, a value list andcount array and the like are formed in the other PMM “k.” Note that thisPMM “k” may be a PMM other than PMM 1 through PMM 4, but of course itmay also be one of PMM 1 through PMM 4.

FIG. 33 is a flowchart showing the compiling according to thisembodiment. Note that in order to simplify the description, considerthat the elements are divided among PMM 1 through PMM 4 as shown in FIG.34A and that the process of assigning sequence numbers among them hasalready been executed. First, each PMM is provided with asequence-number counter that indicates the sequence number of the value(element) subject to processing, a value-number counter that indicatesthe sequence number of the value (element) in question after processing,an identical value counter that indicates how many redundant copies ofthe element in question are present, and a previous-value storageregister that that holds the previous value (element) subject toprocessing (see Step 3301 and FIG. 34A). Note that initially, theprevious-value storage register holds no value.

Thereafter, the processing of Steps 3302-3306 of FIG. 33 is nearlyidentical to that of Steps 2401-2406 of FIG. 24. To wit, each PMM refersto the sequence number counter, identifies the sequence numbers that aresubject to processing, and determines whether or not the elements giventhose sequence numbers are managed by itself (Step 3303). In the stateof FIG. 34A, the value of the sequence number counter is “0” so PMM 3creates a local PMM internal count that indicates how many elements withthe sequence number “0” on the second bus the PMM 3 in question has (inthis example, “1”) (see Step 3306 and FIG. 34B). Next, PMM 3 comparesthe element stored in the previous-value storage register against theelement released on the first bus, and if they are different, sets thevalue of the value-number counter to that sequence number as if it wassent on the first bus (Step 3307). Note that in the state of FIG. 34A,the value of the value-number counter is the initial value of “0” so thesequence number applied to the element “Carter” does not change (seeFIG. 34B).

Next, each PMM receives data given via the first bus (Step 3308). Theprocessing of Steps 3308-3311 is nearly identical to that of Steps2408-2411 of FIG. 24. To wit, each PMM adds the PMM internal count ofthe given data to the value of the sequence-number counter, andmoreover, if the element is not new within the given data (No in Step3310), it adds the PMM internal count to the value of theidentical-value counter (see Step 3311 and FIG. 34B). As shown in FIGS.34A and 34B, when the processing of the element “Carter” with thesequence number of “0” is complete, the processing of the element withthe sequence number of “1” is executed in the same manner (see FIG.35A).

Furthermore, the processing of the element with the sequence number of“2” is executed. Here, PMM 1 compares the element “Carter” stored in theprevious-value storage register against the element “Clinton” with thesequence number of “2.” Here, they are different (Yes in Step 3304), soPMM 1 sends over the second bus the element stored in the previous-valuestorage register and the value of the identical-value counter (Step3305). Next, the PMM 1 sends over the first bus the element “Clinton”subject to processing and the local PMM internal count “1” (Step 3306).Thereafter, PMM 1 compares the element stored in the previous-valuestorage register and the element released on the first bus. In the casethat the element “Clinton” is released, these are different, so thesequence number of the element “Clinton” is set to the value of thevalue-number counter to which “1” is added (0+1=1).

Each PMM receives the data given via the first bus (Step 3308) and addsto the value of the sequence number counter the local PMM internal countwithin the received data (2+1=3) (see Step 3309 and FIG. 35B). In thecase that the element “Clinton” is given, the element “Carter” of theprevious-value storage register and the given element “Clinton” aredifferent (Yes in Step 3310) so each PMM executes the new-valueregistration process (Step 3312). In this process, the value of thevalue-number counter is incremented (0+1=1), the value of theidentical-value counter is changed to the local PMM internal count “1”within the received data, and the content of the previous-value storageregister is rewritten to the element “Clinton” (see FIG. 35B).

The same process is performed on the element “Clinton” with the sequencenumber “3.” For example, PMM 3 may send over the first bus the element“Clinton” and the local PMM internal count “1” (see Step 3306) and setthe sequence number of the element “Clinton” in question to the value“1” of the value-number counter (see Step 3307 and FIG. 36A). Inaddition, each PMM adds to the value of the sequence-number counter thereceived local PMM internal count “1” (see Step 3309) and also adds tothe value of the identical-value counter the local PMM internal count“1” (see Step 3311 and FIG. 36A). Moreover, as shown in FIG. 36B,regarding the element “Johnson” with the sequence number “4” also, thePMM 1 sends over the second bus the element “Clinton” and the value “2”of the identical-value counter (Step 3305), and sends over the first busthe element “Johnson” and the local PMM internal count “1” (Step 3306),and sets the sequence number of the element “Johnson” to the value ofthe value-number counter to which “1” is added (1+1=2). On the otherhand, each PMM executes the incrementing of the sequence-value counterand the new-value registration process (Steps 3309 and 3312 and FIG.36B). The same process is performed for the elements with other sequencenumbers. The processing of the various elements is shown in FIG. 37A andFIG. 38. Note that regarding FIG. 38, the PMM 1 sends the last element“Johnson” and the count of those elements over the first bus and sendsdata that indicates the end over the second bus (see Step 3315).

As described above, the inputs of PMM “k” are connected to the secondbus. Accordingly, non-redundant elements and the value of thevalue-number counter related thereto are given over the second bus.Accordingly, the PMM “k” receives them and places the received elementssequentially in the value list and also places the received values ofthe value-number counter sequentially in the count array. FIG. 39A is adiagram of a value list and count array created within the PMM “k.”These are sent in Step 3305 or Step 3314 (see FIG. 35B, FIG. 36B andFIG. 38) and transmitted to PMM “k.” As shown in FIG. 39A, elements areplaced in the value list without redundancy and counts that indicate thenumber of each element present (namely the redundancy) are placed in thecount array.

Moreover, it is possible to create in PMM 1 through PMM 4 an array ofpointers to the value list that indicates the correspondence betweenrecords and the sequence numbers applied to each element withoutredundancy. To wit, by creating an array that indicates thecorrespondence between the records and the sequence number applied tothe element corresponding to the record in question, it is possible tomake this an array of pointers to the value list (see FIG. 39B). In FIG.39B, regarding record “0,” the sequence number “2” of the correspondingelement becomes the pointer value in the array of pointers to the valuelist. This indicates that, in the value list (see FIG. 39A), the valuesuch that the storage position number is “2” is to be pointed at. Towit, based on the pointer value in the array of pointers to the valuelist, the value list stored in PMM “k” can be pointed at, and thus it ispossible to identify the element from the record.

By means of this embodiment thus described, the elements of an arraydivided among PMMs are sorted and given sequence numbers and, thesequence is reassigned so that the same sequence is assigned to the sameelement. A correspondence is found between elements and a newly obtainednon-redundant sequence and the elements are stored in the value list.The sequence in question is the correspondence between the array ofpointers to the value list and the elements within the divided array.Accordingly, it is possible to identify elements within the value listbased on records via the pointer values in the pointer array.

[Joining a Value List (Embodiment 4)]

Here follows a description of Embodiment 4 of the present invention. InEmbodiment 4, two arrays are joined. This is premised upon the valuelist and array of pointers to the value list being created by compiling.In addition, a space ID is applied the value list and array of pointersto the value list, and various information regarding the part of thearray managed by itself is managed by this space ID in question, etc.

FIG. 40 is a flowchart that shows the joining process according toEmbodiment 4.

In order to simplify the description, as shown in FIG. 41A, consider thecase in which the original data is an array consisting of elementscorresponding to records (see symbol 4100) which is divided over acertain PMM group. Compiling this record group results in the creationof a block (hereinafter referred to as an “information block”)consisting of a pointer array (see symbol 4101) and value list (seesymbol 4102) in the PMM group consisting of PMM 1 and PMM 2. On theother hand, the other arrays consisting of elements corresponding torecords (see symbol 4110) are divided among other PMM groups, and bycompiling, the information block consisting of the pointer array (seesymbol 4111) and value list (see symbol 4112) is created in the PMMgroup consisting of PMM 3 and PMM 4.

The CPU 12 transmits to each PMM an instruction that orders the joiningof the value lists along with the space ID of the array that indicatesthe two value lists. Among the PMMs, those in which the arrays to bejoined are value lists that they manage themselves, or portions thereof,identify the value list subject to joining based on the space ID (seeStep 4001 and FIG. 42A). Next, PMM 1 through PMM 4 sort them in thestate in which the two value lists are merged and assign sequencenumbers to the elements (Step 4002). The sorting according to Embodimentcan be used for this sorting. In the aforementioned example, first, thesequential numbering of elements is executed on the first PMM group madeup of PMM 1 and PMM 2 and the second PMM group made up of PMM 3 and PMM4, and then sequence numbers are applied to the elements within the twoPMM groups by taking the first PMM group as the former PMM group and thesecond PMM group as the latter PMM group. FIG. 42B is a diagram thatshows the state in which the sequence numbers are applied to elements inthis manner.

Thereafter, compiling of the PMMs in which the value lists subject toprocessing are divided is executed to generate a joined value list andjoined count array in another PMM or one of the PMMs 1 through 4 (Step4003). To wit, the compiling is performed to obtain a new value list inwhich the elements of the merged value list are not redundant and acount array that contains counts that indicate how many duplicateelements are present (sec FIG. 42C). After this process, a new pointerarray is needed to point to the joined new value list (namely, the valuelist obtained by compiling). This is achieved by creating a new pointerarray that stores sequence numbers corresponding to the sequence numberarray obtained by compiling, which indicate the pointer values withinthe pointer array in the information block prior to joining, inpositions corresponding to the positions of pointer vales within thepointer array in question. The values within the aforementioned sequencenumber array are understood to correspond to the new sequence numbers(see FIG. 42C) applied to the elements.

As shown in FIG. 43A, for example, the value (sequence number) withinthe sequence number array at the position that indicates the firstpointer value “1” within the pointer array is “2” so the pointer valueat the corresponding position within the pointer array after joiningbecomes “2.” In addition, the value (sequence number) within thesequence number array at the position that indicates the second pointervalue “2” within the pointer array is “3” so the pointer value at thecorresponding position within the pointer array after joining becomes“3.” In this manner, it is possible to obtain a pointer array for thejoined value list (FIG. 43A and FIG. 43B).

In this manner, it is clear that the value (element) can be identifiedfrom the record by means of the new pointer array and joined value list.As shown in FIGS. 44A and 44B, the pointer value at the correspondingposition within the newly obtained array of pointers to the value listis identified and this pointer value identifies the element within thevalue list at the position indicated by that value. Here, one can seethat the same element is specified as in the element of the originaldata, even though two value lists are joined.

In this manner, according to Embodiment 4, by merging a plurality ofvalue lists and combining the sorting and compiling with regard to theelements of the merged value list, it is possible to obtain a joinedvalue list and sequence number array for each value list. The value(sequence number) of the sequence number array is identified by means ofthe pointer array used to specify the value list from a record, and thesequence number in question is stored at a position corresponding to therecord, so a new pointer array can be obtained to specify the joinedvalue list based on the record. Accordingly, it is possible to join aplurality of value lists in roughly the time required for theaforementioned sorting and compiling, so the processing speed can bemarkedly increased.

The present invention is in no way limited to the aforementionedembodiments, as various modifications are possible within the scope ofthe claims, and it need not be said that these are still included withinthe scope of the present invention.

For example, while the present invention was applied to a computersystem in the aforementioned embodiments, but this is not a limitation,as it may also be applied to a computer board that can be connected to apersonal computer or the like. In this case, in FIG. 1, the CPU 12,memory units 14, bus 24 and the like may be mounted upon the board,thereby constituting an information processing unit according to thepresent invention.

In addition, the number of sets of buses that connect the CPU 12 andmemory modules 14, and/or the memory modules 14 to each other is notlimited to those in the aforementioned embodiments, but rather thisnumber may be determined appropriately in consideration of the size ofthe circuit board on which the computer system is mounted, the bit widthof the various buses and the like. In addition, in the aforementionedembodiment, switches 28 for setting the connections between memorymodule input/output and the buses and switches 30 that are able toswitch buses between the CPU and memory modules and among memory modulesare provided. By providing switches 29 and 30, for example, a certainbus (see bus 24-4 of FIG. 1) can be used for both the exchange of databetween the CPU module 12 and memory module 14-1, it can also be usedfor the exchange of data between memory module 14-2 and memory module14-3 (in this case, it is sufficient to turn switch 30-5 off).Accordingly, the buses can be utilized effectively. However, in the casein which the number of sets of buses can be made large enough, or in thecase that the number of memory modules is relatively few, the switches30 need not necessarily be provided.

In addition, this Specification recites that the instructions from theCPU 12 are given via the signal control line 25, but in addition to theinstructions, naturally clock signals or various other control signalsfor making the various memory modules to operate synchronously may alsobe given via the signal control line 25, and also stipulated signalsfrom the various memory modules to the CPU 12 (for example, errorsignals and signals that indicate the receipt of data) may be given.

Moreover, in the aforementioned embodiments, various examples ofconnections among the PMMs are illustrated, but the selections of busesto be used for connections among PMMs and the exchange of signals arenot limited to those illustrated in the aforementioned embodiments.

In addition, in the aforementioned Embodiment 3, as shown in FIG. 32,the first bus (see symbol 3201) is used to perform communication amongPMMs and the second bus (see symbol 3202) is used to perform thecommunication of elements and the count (redundancy) of these elements,but this is not a limitation. For example as shown in FIG. 45, it may bepossible for the PMM “k” which generates a value list which is an arrayof elements with no redundancy and a count array thereof monitor thefirst bus 4501 and, based on the elements and count array appearing uponthe first bus 4501, perform the stipulated processing (e.g., theincrementing of counters and the saving/updating the content ofregisters executed by PMM 1 through PMM 4), thus creating the value listand count array.

Moreover, in this Specification, the function of one means may beimplemented by two or more physical means, or the functions of two ormore means may be implemented by one physical means.

By means of the present invention, it is possible to provide aninformation processing apparatus wherein the sorting, compiling andjoining of arrays can be performed at extremely high speed and withstable processing times.

APPLICABILITY OF THE INVENTION

The present invention is usable in systems that handle large amounts ofdata, for example, databases and data warehouses. More specifically, itis usable in large-scale scientific and technical calculation, and toorder management and the management of mission-critical clerical worksuch as securities trading.

1. A distributed memory type information processing system comprising: aCPU module, a plurality of memory modules, each of which having aprocessor and RAM core, and a plurality of sets of buses that makeconnections between said CPU and memory modules and/or connections amongmemory modules, where the processors of the various memory modulesexecute the processing of arrays managed by the aforementioned one ormore memory modules based on instructions given by the CPU to theprocessors of the various memory modules, wherein said informationprocessing system is characterized in that the processor of said memorymodule comprises: sorting means that executes a sort on the elementsthat make up those portions of the array that it itself manages, andreorders said elements according to a specific order, I/O that,depending on the positions that said portions managed by itself occupywithin the array, sends said sorted elements together with theirsequence numbers to another memory module via a stipulated bus, orreceives said elements and sequence numbers from another memory modulevia a stipulated bus, sequence number calculation means that, uponreceipt of said element and sequence number, compares it with theelements that it manages itself and calculates a virtual sequence numberwhich is a candidate for the sequence number of the received element,and returns it to said other memory module, and sequence determinationmeans that, upon receipt of said virtual sequence number, determines thesequence of elements according to said virtual sequence numbers; suchthat the sequence numbers of elements of said array are determined bymeans of communication between a presentation memory module on the sidethat sends said element and sequence number and a determination memorymodule on the side that receives said element and sequence number andcalculates the virtual sequence number.
 2. The information processingsystem according to claim 1, wherein said memory module comprises:element identification/sending means that identifies elements subject toprocessing according to the determined sequence number and sends it overone of the buses, element comparison means that compares the previouselement subject to processing against the sent element, and anidentical-value counter that indicates the count of identical elementsand whose value is incremented when an identical element is sent;wherein said element comparison means is constituted such that when theprevious element subject to processing is determined to be differentfrom the sent element, the previous element subject to processing isassociated with the value of the identical-value counter related to theelement in question and one of which is sent, and moreover, one of thememory modules receives the previous element subject to processing andthe value of the related counter thus sent, and is provided with anarray in which they are associated and placed in the order received. 3.The information processing system according to claim 2, wherein saidmemory module comprises: a value-number counter that indicates thenon-redundant sequence numbers, whose value is incremented in the eventthat said element comparison means determines that the previous elementsubject to processing is different from the sent element, and sequencenumber updating means that, regarding the sent element, if the previouselement subject to processing is identical to the sent element, sets thevalue of the value-number counter as the sequence number of thenon-redundant element in question, but if they are different, sets theincremented value of the value-number counter as the sequence number ofthe non-redundant element in question.
 4. A method of sorting arraysusing a distributed memory type information processing systemcomprising: a CPU module, a plurality of memory modules, each of whichhaving a processor and RAM core, and a plurality of sets of buses thatmake connections between said CPU and memory modules and/or connectionsamong memory modules, where the processors of the various memory modulesexecute the processing of arrays managed by the aforementioned one ormore memory modules based on instructions given by the CPU to theprocessors of the various memory modules, wherein said method of sortingcomprises: (a) a step of sorting the elements that make up thoseportions of the array that it itself manages in the memory module, (b) astep of, depending on the positions that said portions managed by itselfoccupy within the array, determining, among the memory modules thatmanage portions of said array, a presentation memory module on the sidethat sends the element and sequence number, and a determination memorymodule on the side that receives said element and sequence number, (c) astep of, in the presentation memory module, transmitting the sortedelement together with its sequence number to the other memory module viaa stipulated bus, (d) a step of, in the determination memory module,receiving said element and its sequence number from the other memorymodule via a stipulated bus, (e) a step of, in said determination memorymodule, based on the sequence numbers of elements managed by saiddetermination memory module, calculating a virtual sequence number thatindicates a candidate for the sequence number of the received element,and returning said virtual sequence number to said presentation memorymodule, and (f) a step of, in said presentation memory module, uponreceiving said virtual sequence number, updates the sequence number ofthe element according to said virtual sequence number, and (g) upon eachcompletion of said steps (d) through (f), by taking each of the memorymodule groups consisting of the presentation memory module anddetermination memory module pertaining to the element that is given astipulated sequence number by means of said steps (d) through (f) as oneof the presentation memory module group and determination memory modulegroup, respectively, and repeating steps (d) through (f) to update thesequence numbers of elements in each memory module group, the sequencenumbers of each element of the array are determined.
 5. The method ofsorting according to claim 4, wherein said step (e) comprises: (e1) astep of calculating the virtual sequence number based on a forwardinsertion number that indicates the number of elements to be inserted infront of the received element, the sequence number regarding the elementto be positioned in front, and the received sequence number.
 6. Themethod of sorting according to claim 4 or 5, wherein said step (f)comprises: (f1) a step of setting the received virtual sequence numberto the sequence number of the element sent in step (c).
 7. The method ofsorting according to claim 4, further comprising: (h) a step of, in saidpresentation memory module, calculating the redundancy which indicateshow many elements managed by memory modules that make up saidpresentation memory module group are present within said memory modulegroup, wherein said step (c) comprises: (c1) a step of transmitting thesorted element together with its sequence number and redundancy to theother memory module so that identical elements are not transmittedredundantly, wherein said step (c) comprises: (c1) a step of calculatingthe virtual sequence number based on a forward insertion number thatindicates the number of elements to be inserted in front of the receivedelement, the sequence number regarding the element to be positioned infront, and the received sequence number and redundancy, and wherein saidstep (f) comprises: (f2) a step of deciding the sequence number of theelement identical to the element in question based on the differencebetween the virtual sequence number and the sequence number at the timeof sending of the element in step (c).
 8. The method of sortingaccording to any of claims 4-7, wherein the presentation memory moduleis initially an independent memory module and the receiving module isalso an independent memory module, and the presentation memory modulegroup consists of 2^(n) memory modules where n (n: an integer greaterthan or equal to 1) is incremented each time steps (d) through (f) arecomplete, while the determination memory module group consists of 2^(n)memory modules.
 9. A compiling method wherein an array is sorted bymeans of the method according to one of claims 4-6, and based on saidsorted array, a new array is generated such that the elements withinsaid array are placed in the stipulated order without duplication, andwherein said compiling method comprises: (i) a step of, in thestipulated memory module, sending the elements subject to processingaccording to the sequence number, (j) a step of, if the previous elementsubject to processing is identical to the sent element, incrementing theidentical-value counter that indicates the count of the identicalelements present, but if an element different from the previous elementsubject to processing was sent, associating the previous element subjectto processing with the value of the identical-value counter related tothe element in question and sending these, (k) a step of receiving theprevious element subject to processing and the value of the associatedidentical-value counter, and generating a new array which has themassociated, and (l) repeating steps (i) through (j) to place theelements and their counts such that they are associated in said newarray.
 10. The compiling method according to claim 9, further comprising(m) a step of, in one of the modules, monitoring the element sent instep (j) and the value of the associated identical-value counter, andwherein step (k) is executed by means of one of said modules.
 11. Thecompiling method according to claim 9, further comprising (n) a step of,in the memory modules that manage the elements of said array, providinga sequence-number counter and identical-value counter that hold thesequence number of the element subject to processing and the count ofsaid elements, respectively, and also providing a register thattemporarily stores the previous element subject to processing, (o) astep of, in the memory module that manages the element having thesequence number in question, sending the element in question accordingto the sequence number, (p) a step of, in the memory module that managesthe elements of the array, comparing the received element and thecontent of the register, and if these are identical, incrementing thecount, but if they are not identical, sending the content of theregister and the value of the counter over the second bus, and thenupdating the content of the register and the value of the counter, (q) astep of, in one of the memory modules, placing the content of saidregister and the value of said counter as the element and count of saidelements, respectively, in the array.
 12. The compiling method accordingto claim 11, wherein step (n) further comprises: (n1) a step ofproviding a value counter that stores non-redundant sequence numbers forelements subject to processing, wherein said step (p) comprises: (p1) astep of comparing the received element and the content of the register,and if these are identical, assigning the value of the value-numbercounter as the sequence number of said element subject to processing,but if they are not identical, incrementing the value-number counter,and assigning the value of the incremented value-number counter as thesequence number of said element subject to processing.
 13. A method ofjoining arrays that achieves the joining of a plurality of arrays usingthe sorting method according to one of claims 4-8 and the compilingmethod according to one of claims 9-12, wherein said joining methodcomprises: (r) a step of merging a plurality of arrays and executing theprocessing of said sorting method by assigning sequence numbers to eachof the elements in these arrays, and (s) a step of executing theprocessing of said compiling method according to the elements withinsaid merged array and their sequence numbers, thereby generating a newarray with no redundant elements present.
 14. A method of joining arraysthat achieves the joining of a plurality of arrays using the sortingmethod according to one of claims 4-8 and the compiling method accordingto one of claims 9-12 using a distributed memory type informationprocessing system comprising: a CPU module, a plurality of memorymodules, each of which having a processor and RAM core, and a pluralityof sets of buses that make connections between said CPU and memorymodules and/or connections among memory modules, where the processors ofthe various memory modules execute the processing of arrays managed bythe aforementioned one or more memory modules based on instructionsgiven by the CPU to the processors of the various memory modules,wherein said memory modules each comprises a pointer array in whichpointer values indicating a value list are placed at positionscorresponding to the record number in order to specify stipulatedelements in the value list which is an array that stores elements basedon the record number, and said method of joining comprises: (r1) a stepof merging a plurality of value lists and executing the processing ofsaid sorting method by assigning sequence numbers to each of theelements in theses arrays, and (t) a step of executing the processing ofsaid compiling method according to the elements within said merged valuelist and their sequence numbers, thereby generating a new array with noredundant elements present and also updating the sequence numbers ofsaid elements to the sequence numbers of said elements in the case thatno redundant elements are present, and (u) a step of setting said arrayconsisting of sequence numbers of elements in the case in which noredundant elements are present as a new pointer array for indicating thenew value list.